Electronic devices, such as mobile phones, personal computers, personal digital assistants, and many others, utilize processors, memories, input/output (I/O) and other digital devices in order to provide their designed functionality to end users. These various digital devices are connected to one another using interconnects (also sometimes referred to as “busses”), which convey data, signals and commands between or among the various devices. When one device begins to transmit such data, signals and commands (herein sometimes referred to generically as “data”) to another device over the interconnect, a link startup process is used to transition the two devices from their initially uncommunicative state to a state in which they are actively communicating with one another over the then setup link. Link startup processes, as with other processes performed over such interconnects, are sometimes defined by one or more standards which are promulgated to specify interconnects.
For example, in the Mobile Industry Processor Interface Alliance (MIPI), several standards are defined. One of these standards is called UniPro (Unified Protocol), which is aimed at chip-to-chip networks using high-speed serial links. UniPro is defined to be a general purpose protocol that solves the general interconnect problems, such as error handling, flow control, routing or arbitration. UniPro is intended to increase the flexibility of phone manufacturers by mixing and matching chips with different functionalities, potentially from different vendors for easy creation of new devices.
UniPro currently supports D-PHY links, which are high-speed, serial, low-power PHY links using separate clock and data lanes. Starting from version 1.40, UniPro will offer M-PHY support, which further embeds the clock in the data lanes. M-PHY will offer two transmission modes: low speed and high speed, each supporting multiple speed gears, and will also support several power-save states: STALL for the high-speed mode, SLEEP for the low-speed mode, and HIBERN8. STALL and SLEEP are optimized for a quick wakeup in their respective transmission modes, whereas HIBERN8 is a very low-power mode, which has a longer wakeup time. M-PHY is also defined to support optical links. In this document, a UniPro and PHY combination is called a UniPort, which has two flavours: UniPort-D and UniPort-M for D-PHY and M-PHY, respectively.
M-PHY in UniPro will differ from other existing high-speed, embedded-clock PHYs used in interconnects, such as those defined in standards commonly referred to as PCI Express, RapidIO and HyperTransport, as it is optimized for low power. Even though PCI Express, RapidIO and HyperTransport have power-save states, they only have one transmission mode, as opposed to M-PHY, which will have high-speed (also higher power) and low-speed (also lower-power) transmission modes. This makes the M-PHY control in UniPro more complex, as all of the states needed to support two transmission modes have to be managed. To understand better the challenge associated with link startup in UniPro based interconnects, a discussion of link startup in PCI Express, RapidIO and HyperTransport will now be provided.
For example, PCI Express uses a serial embedded-clock PHY that transfers data at potentially multiple speeds, and has power save states. PCI Express starts operating in its lowest transmission mode, i.e., at 2.5 GHz, and supports links up to 32 lanes, in powers of two. Both directions of the link have the same number of lanes, numbered identically, and all lanes always have the same power and transmission speed. The link startup in PCI Express is called “Link Training”, and consists of 3 states: (1) the Detect State, in which a PCI Express port detects the presence of a peer port and the number of connected lanes (this is done by the Tx electrically detecting the presence of a termination impedance, which implies a peer Rx), (2) the Polling State, in which the two ends of a link use handshakes to determine their maximum common speed and detect the correct signal polarity, and (3) the Config State, in which the number of links (in the case of a downstream port) and the number of lanes and lane numbering (for both downstream and upstream ports) are determined (this is done by the upstream device (using its downstream port) iteratively sending training sequence ordered sets (TS1 OS), which are responded to by the downstream device which receives a TS1 OS with a Lane 0 label). At each iteration, the upstream device renumbers its downstream lanes based on the information it received from its peer downstream devices, such that, in the end, all downstream devices will be given a set of lanes numbered consecutively starting with 0.
However, the UniPort-M link startup process will need to differ from the PCI Express Link Training in that, among other things, the detection step cannot be performed electrically, because the UniPort-M's initial transmission mode uses the low power transmission mode, which has no termination impedance. As a result, as opposed to PCI Express, UniPort-M's lane detection should be performed using a protocol rather than electrical detection. Additionally, unlike PCI Express, the M-PHY of UniPro will start in the HIBERN8 power-save state, and needs to be configured to transition to a transmission mode. Additionally, UniPorts will be more flexible in the manner in which the lanes are interconnected since UniPro will support asymmetrical links (i.e., different number of lanes in the two directions). Accordingly, the link startup protocol of PCI Express is not suitable for link start up of M-PHY links in UniPro.
Turning now to Serial RapidIO, also sometimes referred to as RapidIO in this document, this bus standard supports an embedded-clock PHY that transfers data at potentially multiple speeds. No power save state is specified. If baud rate discovery is supported, RapidIO starts transmitting data at its highest supported speed. The node which detects a lower incoming data transmission will lower its transmission rate until both nodes have the same transmission rate. RapidIO supports up to 16 lanes, in powers of two. Both directions of the link have the same number of lanes, numbered identically, and all lanes always have the same power and transmission speed.
A multi-lane RapidIO link startup process, called the “port initialization process”, consists of four or more secondary state machines, specifically:
(1) the Lane Synchronization state machine is used by each lane individually to achieve bit and symbol synchronization at the Rx side by counting comma and valid symbols up to 127 and Vmin, respectively;
(2) the Lane Alignment state machine is used for a multi-lane link to achieve Rx lane alignment by monitoring PHY symbol patterns to detect and eliminate inter-lane skew;
(3) the 1×/2×_Mode_Detect state machine is a RapidIO specific step that detects whether a 2× link is used in a 1× mode (using one lane for data and one lane for redundancy, the redundancy lane is used by RapidIO to transmit data of a lane which is physically broken, and still offer a lower-speed connectivity if such faults occur) or a 2× mode (using both lanes for data); and
(4) the 1×/N× Initialization state machine starts with detecting a peer device by exchanging idle sequences on lanes 0 and 2. After a peer device is detected, the idle sequences are sent on all N lanes. If the peer device responds on all N lanes, the device enters the N× transmission mode, where all lanes are used. If not all incoming lanes carry data, one lane is used: either lane 0, if usable, or the redundancy lane if lane 0 is not useable. If more than one multi-lane transmission mode is supported, link width negotiation is used to select the greatest link width supported by both endpoints.
In contrast to RapidIO, and as mentioned previously, UniPort-M will start in a HIBERN8 state. Additionally, UniPorts are more flexible in the manner in which the lanes are interconnected since UniPro will support asymmetrical links (i.e., different number of lanes in the two directions). Accordingly, the link startup protocol of RapidIO is also not suitable for M-PHY in UniPro.
Turning thirdly to the bus standard known as HyperTransport Gen3, also sometimes referred to as HyperTransport in this document, this bus standard uses an embedded-clock PHY that offers data transmission at potentially multiple speeds, and has power save states. HyperTransport supports links with up to 32 lanes in powers of two. The link width is auto-negotiated. The lanes on both directions are statically numbered. The two link directions can be configured by software to have different widths.
A characteristic of HyperTransport is the use of CTL (control) lanes in addition to the usual CAD (clock & data) lanes. CTL lanes are used to indicate when control packets are transmitted and to improve the link robustness to transmission errors. Given the presence of CTL lanes, HyperTransport does not use the 8b10b K-codes, which are normally used for control, except for link training
A multi-lane HyperTransport link startup, called Initialization, first electrically detects the peer device, then uses the 1200 MHz transmission mode for a series of Training 0-3 phases which use Training Patterns to establish bit and byte synchronization. The speed is not negotiated, but can be configured using software later. The link width is negotiated up to 8 lanes. The lane width can be configured via software, including using 16 or 32 lanes if that's supported by the 2 devices. Also asymmetrical link usages are possible through software. HyperTransport does not enumerate lanes.
Again, unlike HyperTransport, UniPort-M devices start in a HIBERN8 state. Additionally, unlike HyperTransport, UniPro will support automatic lane enumeration to ease chip-to-chip interconnect layout. Accordingly, the link startup protocol of HyperTransport is also not suitable for M-PHY in UniPro.
Accordingly, it would be desirable to provide methods, nodes and systems for interconnect link startup, e.g., for M-PHY links in UniPro systems.